Template:Intel processor roadmap
|
|---|
| Atom (ULV)
| 製造プロセス
| x86
|
|
|
| 600 nm
| P6
| Pentium Pro
(133 MHz)
|
|
|
| 500 nm
| Pentium Pro
(150 MHz)
|
|
|
| 350 nm
| Pentium Pro
(166–200 MHz)
|
|
|
| Klamath
|
|
|
| 250 nm
| Deschutes
|
|
|
| Katmai
|
| NetBurst
|
|
|
| 180 nm
| Coppermine
|
| Willamette
|
|
|
| 130 nm
| Tualatin
|
| Northwood
|
|
|
| Banias
|
|
| NetBurst(HT)
|
| NetBurst(×2)
|
|
| 90 nm
| Dothan
|
| Prescott
| ⇨
| Prescott‑2M
| ⇨
| Smithfield
|
|
|
| Tejas
| →
| ⇩
| →
| Cedarmill (Tejas)
|
|
| 65 nm
| Yonah
|
| Nehalem (NetBurst)
|
| Cedar Mill
| ⇨
| Presler
|
|
| Core
| Merom
| (x86-64) DDR2 + DDR3
|
| Bonnell
| Bonnell
| 45 nm
| Penryn
|
|
| Nehalem
| Nehalem
| HT再導入, メモリコントローラ統合, PCH,
L3キャッシュ導入, 256 KiB L2キャッシュ/コア, DDR3
|
| Saltwell
| 32 nm
| Westmere
| CPUパッケージに45 nmGPUを統合, AES-NI導入
|
| Sandy Bridge
| Sandy Bridge
| リングバス, GPU on die, 非UEFIマザーボードの終焉, DDR3
|
| Silvermont
| Silvermont
| 22 nm
| Ivy Bridge
|
|
| Haswell
| Haswell
| FIVR, DDR3 + DDR3L
|
| Airmont
| 14 nm
| Broadwell
|
|
| Skylake
| Skylake
| DDR3L + DDR4
|
| Goldmont
| Goldmont
| Kaby Lake /
Amber Lake
|
|
| Goldmont Plus
| Coffee Lake
| 8コア (デスクトップ)
|
| Whiskey Lake
|
|
| Comet Lake
| 10コア (デスクトップ)
|
| Cypress Cove
| Rocket Lake
|
|
| Tremont
| Tremont
| 10 nm
| Palm Cove
| Cannon Lake
|
| SoC
|
|
| Sunny Cove
| Ice Lake
| 512KiB L2キャッシュ/コア
| Lakefield
|
|
| Willow Cove
| Tiger Lake
| Xe グラフィックス
|
|
| Gracemont
| Gracemont
| Intel 7
| Golden Cove
| Alder Lake
| Hybrid, DDR5, PCIe 5.0
|
|
| Raptor Cove
| Raptor Lake
| 2MiB L2キャッシュ/Pコア
|
|
取消線nameは計画中止
- 太字nameはマイクロアーキテクチャ名
- 斜体nameは将来の計画
|
画像版
